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This X24026 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
2K
X24026
Serial E2PROM
DESCRIPTION
256 x 8 Bit
FEATURES
*2.7V to 5.5V Power Supply *Low Power CMOS --Active Current Less Than 1mA --Standby Current Less Than 50A *Internally Organized 256 x 8 *Self Timed Write Cycle --Typical Write Cycle Time of 5 ms *2 Wire Serial Interface --Bidirectional Data Transfer Protocol *Four Byte Page Write Operation --Minimizes Total Write Time Per Byte *High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years
The X24026 is a CMOS 2048 bit serial E PROM, internally organized 256 x 8. The X24026 features a serial interface and software protocol allowing operation on a simple two wire bus. Xicor E PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DICE form with ISO 7816 compatible pin out.
2
2
--ESD Protection > 2KV
FUNCTIONAL DIAGRAM
V CC V SS
START CYCLE SDA
START STOP
H.V. GENERATION TIMING
& CONTROL LOGIC
CONTROL LOGIC
SLAVE ADDRESS REGISTER
SCL
+COMPARATOR
LOAD
INC
XDEC
E PROM 64 X 32
2
WORD ADDRESS COUNTER
R/W
YDEC 8 CK PIN DATA REGISTER
D OUT
D
OUT ACK
7020 FRM 01
Xicor, Inc. 1994, 1995, 1996 Patents Pending 7020-1.2 2/24/97 T1/C0/D2 SH
1
Characteristics subject to change without notice
X24026
PIN DESCRIPTIONS
Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
SDA
DIE CONFIGURATION
VSS
VCC
SCL SDA
X24026 Die Revision A .055 x .079
7020 FRM 02
PIN DESCRIPTIONS Symbol
SDA SCL
VSS VCC
Description
Serial Data Serial Clock Ground +5V
7020 FRM T01
2
X24026
DEVICE OPERATION
The X24026 supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24026 will be considered a slave in all applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
The X24026 continuously monitors the SDA and SCL lines for the start condition and will not respond to any
command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
7020 FRM 03
3
X24026
The X24026 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24026 will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24026 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24026 will continue to transmit data. If an acknowledge is not detected, the X24026 will terminate further data transmissions. The master must then issue a stop condition to return the X24026 to the standby power mode and place the device into a known state.
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24026 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
7020 FRM 04
Figure 3. Acknowledge Response from Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
7020 FRM 05
4
X24026
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave are the device type identifier (see Figure 4). For the X24026 this is fixed as 1010[B]. Following the start condition, the X24026 monitors the SDA bus comparing the slave address being transmitted with its slave address. Upon a correct compare the X24026 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24026 will execute a read or write operation. WRITE OPERATIONS Byte Write For a write operation, the X24026 requires a second address field. This address field is the word address,
0 0 0 0 R/W
Figure 4. Slave Address
DEVICE TYPE IDENTIFIER
1
0
1
comprised of eight bits, providing access to any one of the 256 words of memory. Upon receipt of the word address the X24026 responds with an acknowledge, and awaits the next eight bits of data, again responding with
RESERVE ADDRESS
BITS
7020 FRM 06
an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24026 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24026 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
The next three significant bits are reserved address bits. The last bit of the slave address defines the operation to be performed. When set to one a read operation is selected, when set to zero a write operations is selected.
Figure 5. Byte Write
S T
BUS ACTIVITY: A R MASTER
SLAVE ADDRESS
WORD ADDRESS
DATA
S T
T
O P
SDA LINE BUS ACTIVITY: X24026
S
A C A C A C
P
K
K
K
7020 FRM 07
Figure 6. Page Write
S T
BUS ACTIVITY: A R MASTER
SLAVE ADDRESS
WORD ADDRESS (n)
DATA n
DATA n+1
DATA n+3
S T
T
O P
SDA LINE BUS ACTIVITY: X24026
S
A C A C A C A C A C
P
K
K
K
K
K
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
7020 FRM 08
5
X24026
Flow 1. ACK Polling Sequence
Page Write The X24026 is capable of a four byte page write opera- tion. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24026 will respond with an acknowledge. After the receipt of each word, the two low order address bits are internally incremented by one. The high order six bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address counter will "roll over" and previously written data will be overwritten. As with the the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Acknowledge Polling The disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24026 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24026 is still busy with the write operation no ACK will be returned. If the X24026 has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation. READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a "don't care ." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
WRITE OPERATION
COMPLETED ENTER ACK POLLING
ISSUE START
ISSUE SLAVE_ ADDRESS AND R/W = 0
ISSUE STOP
ACK RETURNED?
NO
YES
NEXT OPERATION
NO
A WRITE? YES
ISSUE BYTE ADDRESS
ISSUE STOP
PROCEED
PROCEED
7020 FRM 09
6
X24026
Current Address Read Internally the X24026 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the X24026 issues an acknowledge and transmits the eight bit word during the next eight clock cycles. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24026 and then by the eight bit word. The master terminates this transmission by issuing a stop condition, omit- ting the ninth clock cycle acknowledge. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
Figure 7. Current Address Read
S T
BUS ACTIVITY: MASTER
A R
SLAVE ADDRESS
DATA
S T
T SDA LINE BUS ACTIVITY: X24026 S
A C
O P
P
K
7020 FRM 10
Figure 8. Random Read
BUS ACTIVITY: A MASTER R
S T
SLAVE ADDRESS
WORD ADDRESS n
S T
A R
SLAVE ADDRESS
DATA n
S T
T SDA LINE BUS ACTIVITY: X24026 S
A C A C
T S
A C
O P
P
K
K
K
7020 FRM 11
7
X24026
The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 255), the counter "rolls over" X24026 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and
Sequential Read Sequential Read can be initiated as either a current address read or random access read. The first word is
transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires
additional data. The X24026 continues to output data for each acknowledge received. The master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge.
data transfer sequence.
Figure 9. Sequential Read
SLAVE ADDRESS
S T O P
BUS ACTIVITY: MASTER
A C
A C
A C
K
K
K
SDA LINE BUS ACTIVITY: X24026
A C
P DATA n DATA n+1 DATA n+2 DATA n+x
7020 FRM 12
K
8
X24026
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................... -65C to +135C Storage Temperature ........................ -65C to +150C Voltage on any Pin with Respect to V SS ............................. -1.0V to +7.0V D.C. Output Current .............................................5 mA Lead Temperature (Soldering, 10 Seconds) ...... 300C
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial
Min.
0C
Max.
70C
7020 FRM T09
Supply Voltage
X24026 X24026-2.7
Limits
4.5V to 5.5V 2.7V to 5.5V
7020 FRM T10
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified).
Limits Symbol
lCC1 lCC2 ISB (1) ISB (2) ILI ILO VlL (2) VIH (2) VOL
Parameter
Power Supply Current (read) Power Supply Current (write) Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
Min.
Max.
1 2 50 30 10 10
Units
mA
Test Conditions
SCL = VCC x 0.1/V CC
100 KHz, SDA = Open x 0.9 Levels @
A A A A V V V
SCL = SDA = VCC - 0.3V, VCC = 5V 10%
SCL = SDA = VCC - 0.3V, VCC = 3V VIN = GND to VCC VOUT = GND to VCC
-1.0 VCC x 0.7
VCC x 0.3 VCC + 0.5 0.4
IOL = 3 mA
7020 FRM T02
CAPACITANCE TA = 25C, f = 1 MHz, VCC = 5V
Symbol
CI/O (3) CIN (3)
Parameter
Input/Output Capacitance (SDA) Input Capacitance (SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
7020 FRM T04
Notes:(1)Must perform a stop command prior to measurement. (2)VIL min. and VIH max. are for reference only and are not tested. (3)This parameter is periodically sampled and not 100% tested.
9
X24026
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Levels
EQUIVALENT A.C. LOAD CIRCUIT
VCC x 0.1 to VCC x 0.9 10 ns
OUTPUT 5.0V 1533
VCC x 0.5
7020 PGM T05
100pF
7020 FRM 13
A.C. CHARACTERISTICS (Over recommended operating conditions) DATA INPUT TIMING
Symbol
fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH
Parameter
SCL Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
Min.
0
Max.
100 100
Units
KHz ns s s s s s s s
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
0.3 4.7 4.0 4.7 4.0 4.7 0 250
3.5
Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
1 300 4.7 300
ns s ns s ns
7020 FRM T06
Bus Timing
tF SCL tSU:STA SDA IN tAA SDA OUT
7020 FRM 14
tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
POWER-UP TIMING Symbol
tPUR(4) tPUW(4)
Parameter
Power-up to Read Operation Power-up to Write Operation
Max. 1 5
Units ms ms
7020 FRM T07
Notes:(4)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
10
X24026
WRITE CYCLE LIMITS Symbol
tWR(6)
Parameter
Write Cycle Time
Min.
Typ.
5
(5)
Max.
10
Units
ms
7020 FRM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK tWR
STOP CONDITION START CONDITION X24026 ADDRESS
7020 FRM 15
Notes:(5)Typical values are for TA = 25C and nominal supply voltage (5V) (6)tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120
RMIN =
SYMBOL TABLE
WAVEFORM INPUTS
Must be steady May change from Low to
OUTPUTS
Will be steady
RESISTANCE (K)
100 80 60 40 20 0 0
RMAX
V CC MAX IOL MIN tR
=1.8K
=
CBUS
MAX. RESISTANCE
Will change from Low to
High
May change from High to
High
Will change from High to
Low
MIN. RESISTANCE
Low
Changing: State Not
Don't Care: Changes
20
40
60
80 100120
Allowed N/A
7020 FRM 16
Known
Center Line is High
BUS CAPACITANCE (pF)
Impedance
11
X24026
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
VCC NC SCL NC
VSS NC SDA NC
SmartCard Module generic
VSS
VCC
X24026
SCL SDA SDA
7020 FRM 17
12
X24026
X24026 SMART CARD TYPE Y
3 MAX. DRAFT ANGLE
3.369 0.002 (85.57 0.05)
(ALL AROUND)
0.593 0.002 (15.06 0.05)
R. 0.125 (3.18) (4x)
0.430 0.002 (10.92 0.05)
A
0.475 0.010 (12.07 0.25)
V CC NC SCL NC
V SS NC
SDA NC
2.125 0.002 (53.98 0.05)
A
R. 0.030 (0.76) (4x)
0.31 0.0005 (.079 0.0127)
0.478 0.002 (12.14 0.05)
MOLD GATE DETAIL SECTION A-A
SCALE: 5x NOTES:
1. ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS). 2. SPECIFIED DIMS ARE MEASURED AT BOTTOM OF CAVITY. 3. MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE. 4. SURFACE FINISH SUITABLE FOR OFFSET PRINTING.
7020 FRM 18
13
X24026
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
0.465 0.002 (11.81 0.05) 0.088 (2.24) MIN EPOXY FREE AREA (TYP.)
0.285 (7.24) MAX.
R. 0.039 (1.00) (4X)
0.069 (1.75) MIN EPOXY FREE AREA (TYP.)
0.270 (6.86) MAX. SEE NOTE 7 SHT 2. 0.420 0.002 (10.67 0.05)
A
A
0.008 0.001 (0.20 0.03)
0.210 0.002 (5.33 0.05)
0.233 0.002 (5.92 0.05)
SECTION A-A
GLOB SIZE FR4 TAPE
DIE
0.0235 (0.60) MAX.
0.015 (0.38) MAX. 0.008 (0.20) MAX.
SEE DETAIL SHEET 3
COPPER, NICKEL PLATED, GOLD FLASH
0.146 0.002 (3.71 0.05)
0.174 0.002 (4.42 0.05)
R. 0.013 (0.33) (8x)
0.105 0.002 TYP. (2.67 0.05)
(8x)
0.105 0.002 (8x) (2.67 0.05)
NOTE: 1.ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
7020 FRM 19
14
X24026
ORDERING INFORMATION 2 X24026: 256 x 8 CMOS Serial E PROM
X24026 Device
P
T
G -V
VCC Range 2.7 = 2.7V to 5.5V
Blank = 4.5V to 5.5V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free
Temperature Range Blank = Commercial = 0C to +70C
Package H = DICE (Waffle Packs)
W = Wafer form X = COB SmartCard Module
Y = ISO, SmartCard
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
15

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